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| Pr el ar in im Semiconductor Semiconductor MSM9554/MSM9555 LSI Devices for FM Multiplex Data Demodulation MSM9554/MSM9555 y GENERAL DESCRIPTION The MSM9554 and MSM9555 are LSI devices which demodulate FM character multiplex signals in the DARC (DAta Radio Channel)*1 format to acquire digital data. The MSM9554 and MSM9555 operate on 5V and 3V, respectively. In the DARC format, baseband signals at ordinary FM broadcasting frequencies are multiplexed with 16k-bps digital data which are L-MSK-modulated at 76kHz. Each of the MSM9554 and MSM9555 has a bandpass filter consisting of SCF, frame synchronization circuit, and error correction circuit, on a single chip. So, a system for acquisition of digital data can be easily constructed by externally mounting an FM receiver tuner, microcontroller for control, and memory for temporary storage of data. The MSM9554 and MSM9555 have a simple configuration, and are equipped with only necessary functions. By making changes to software for the external microcontroller, the MSM9554 and MSM9555 can meet the various requirements of FM multiplex broadcasting services which will be offered in future. These devices are best suited to the car radios and car navigation systems supporting VICSs (Vehicle Information and Communication System)*2 that have been serviced since Aprit, 1996. *1 DARC is a registered trademark of NHK ENGINEERING SERVICES, INC. Note that a contract needs to be made with NHK Engineering Service if a manufacturer produces/ sells electronic equipment utilizing the DARC technology. *2 If samples or detail documents are to be provided, contracts with VICS center are reqired beforehand. FEATURES * Built-in discrambler supporting VICS * Pin compatible with MSM9552/MSM9553 * Built-in bandpass filter (SCF) * Built-in timer internal to block * Built-in block synchronization circuit and frame synchronization circuit * Setting of the number of synchronization protecting stages * Regeneration of data clocks by digital PLL * 1T delay detection * Built-in error correction circuit * Built-in layer 4 and layer 2 CRC check circuit * Microcontroller parallel interface * Clock output for external devices (64kHz to 8.192MHz selectable) * International standard frame format * Power source: 5V (MSM9554), 3V (MSM9555) * Package 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: MSM9554GS-2K/MSM9555GS-2K) 1 2 Limitter AIN LPF Variable gain AMP BPF (SCF) + - Clock regeneration Block synchronization Frame synchronization Timing control Vref SG MSM9554/MSM9555 BLOCK DIAGRAM Filter PN descrambler LSI internal clock DB2 WR31 CLR DVDD D CK Q 1T delay circuit 34Byte RAM 2 VICS descrambler Error correction & Layer 2 CRC Layer 4 CRC Data bus Addressbus Limitter Frequency divider LPF + - CPU interface Digital Signal Processor Semiconductor Delay Detection XOUTC XOUT XTAL2 XTAL1 Data bus DB0-DB7 Address AD0-AD5 RD WR CS CLR INT Semiconductor MSM9554/MSM9555 PIN CONFIGURATION (TOP VIEW) IOWR IORD CLR NC NC NC A5 A4 A3 A2 44 MON ADETIN AVDD AGND SG AIN XOUTC MOUT0 MOUT1 MOUT2 MOUT3 11 12 MOUT4 MOUT5 MOUT6 INT WR NC RD DB0 DB1 DB2 1 34 33 A0 XOUT CS XTAL2 XTAL1 DVDD DGND DB7 DB6 DB5 23 22 DB3 DB4 Note: Leave the NC pins open. 44-Pin Plastic QFP A1 3 MSM9554/MSM9555 Semiconductor PIN DESCRIPTION Function Microcontroller interface Pin 16 18 15 31 40 33 to 38 19 to 26 Tuner interface Analog section test Digital section test 6 5 1 2 41 42 8 to 14 Clock 29 30 32 7 Power supply 3 4 28 27 Symbol WR RD INT CS CLR A0 to A5 DB0 to DB7 AIN SG MON ADETIN IORD IOWR MOUT0 to MOUT6 XTAL1 XTAL2 XOUT XOUTC AVDD AGND DVDD DGND Type I I O I I I I/O I O O I I O I O O I -- -- -- -- Description Write signal to internal register Read signal to internal register Interrupt signal to microcontroller. "L": Occurrence of an interrupt Chip select signal. "L": Read, write, and data bus signals valid "L" initializes internal registers, and the device enters power down mode Address signal to internal register Data bus signal to internal register FM multiplex signal input Analog reference voltage output pin. To prevent noise, connect a capacitor between this pin and analog ground. Analog section waveform monitor pin. The analog block is specified by the analog control register. Analog signal input pin for testing Digital section test signal input pins. Internally pulled up. Digital section test signal output and monitor output pins 8.192MHz crystal oscillator connection pin 8.192MHz crystal oscillator connection pin Pin for supply of 64kHz to 8.192MHz clock to the outside XOUT output control pin. "L"=Clock output, "H"=Output disabled. Pulled up internally. Analog section power supply pin Analog ground pin Digital section power supply pin Digital ground pin 4 Semiconductor MSM9554/MSM9555 ABSOLUTE MAXIMUM RATINGS (MSM9554) Parameter Power supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature Symbol AVDD DVDD VI VO PD TSTG Condition AVDD=DVDD Ta=25C Ta=25C per package Ta=25C per output -- Rating -0.3 to +7.0 -0.3 to AVDD+0.3 -0.3 to DVDD+0.3 400 50 -55 to +150 C V Unit mW RECOMMENDED OPERATING CONDITIONS (MSM9554) Parameter Power supply voltage Crystal frequency FM multiplex signal input voltage Operating temperature Symbol AVDD DVDD fXTAL VAIN TOP Condition AVDD=DVDD -- Composite signals, including multiplex signals -- Range 4.5 to 5.5 8.192MHz 100ppm 0.5 to 2 -40 to +85 Unit V -- VP-P C Applied Pin AVDD DVDD XTAL1 XTAL2 AIN -- ELECTRICAL CHARACTERISTICS (MSM9554) Parameter Current consumption Symbol IDD Condition During operation, No load f=8.192MHz During power down, No load BPF pass band attenuation GAIN1 72 - 80kHz Variable gain amplifier gain: 0dB 0 - 53kHz Variable gain amplifier gain: 0dB 100 - 500kHz Variable gain amplifier gain: 0dB Min. Typ. Max. Unit Applied Pin -- -- -- 18 -- -- 34 20 3.0 mA mA dB MON AVDD DVDD BPF reject band attenuation GAIN2 50 -- -- dB MON BPF reject band attenuation GAIN3 50 -- -- dB MON 5 MSM9554/MSM9555 Semiconductor ABSOLUTE MAXIMUM RATINGS (MSM9555) Parameter Power supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature Symbol AVDD DVDD VI VO PD TSTG Condition AVDD=DVDD Ta=25C Ta=25C per package Ta=25C per output -- Rating -0.3 to +7.0 -0.3 to AVDD+0.3 -0.3 to DVDD+0.3 400 50 -55 to +150 C V Unit mW RECOMMENDED OPERATING CONDITIONS (MSM9555) Parameter Power supply voltage Crystal frequency FM multiplex signal input voltage Operating temperature Symbol AVDD DVDD fXTAL VAIN TOP Condition AVDD=DVDD -- Composite signals, including multiplex signals -- Range 2.7 to 3.3 8.192MHz 100ppm 0.2 to 0.9 -20 to +75 Unit V -- VP-P C Applied Pin AVDD DVDD XTAL1 XTAL2 AIN -- ELECTRICAL CHARACTERISTICS (MSM9555) Parameter Current consumption Symbol IDD Condition During operation, No load f=8.192MHz During power down, No load BPF pass band attenuation GAIN1 72 - 80kHz Variable gain amplifier gain: 0dB 0 - 53kHz Variable gain amplifier gain: 0dB 100 - 500kHz Variable gain amplifier gain: 0dB MIN TYP MAX Unit Applied Pin -- -- -- 14 -- -- 23 10 3.0 mA mA dB MON AVDD DVDD BPF reject band attenuation (1) BPF reject band attenuation (2) GAIN2 50 -- -- dB MON GAIN3 50 -- -- dB MON 6 Semiconductor APPLICATION CIRCUIT MSM9554 or MSM9555 8 bit FM tuner FM multiplex data demodulation device Font ROM SRAM PLL MCU Display MSM9554/MSM9555 Keys 7 |
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